1. Field of the Invention
The present invention relates generally to semiconductor packaging technology and, more particularly, to a method for manufacturing a wafer level chip scale package (WL-CSP).
2. Description of the Related Art
As well known in the art, a great number of integrated circuit (IC) devices are fabricated in a semiconductor wafer and divided into individual chips. The chips are then separated from the wafer and assembled in the package form to be used for electronic systems or products. A package provides in general a structure to mechanically support the chip, a physical housing to protect the chip from the environment, electrical connections to and from the chip, and paths of removing heat generated by the chip.
Recently the rapid growth of multimedia, information, communication, and digital related industries requires new and advanced IC products with small form factor, high integration, and high performance. Such currents of the market are reflected in reduced chip size, increased electrical terminals, and so forth, which result in many new challenges to structural and electrical design of the package rather than of the chip. The packaging technology of today is so getting more important as to affect the price, performance, and reliability of electronic end-applications.
A widely known, initial form of the package has used a lead frame that has lead terminals peripherally arranged at edges of the chip. Thereafter, a ball grid array (BGA) package using solder balls area-distributed over a printed circuit board has been developed to offer a greater number of terminals, and further, a chip scale package (CSP) has been developed to satisfy the industry's growing demand for the smallest, i.e., chip-sized, form factor. Additionally, a wafer level package (WLP) technology has been introduced to realize cost-effective fabrication of packages on the wafer prior to chip separation.
A conventional WLP and its fabrication are shown in FIGS. 1A to 1K. The illustrated, conventional WLP has been well known as ‘ShellBGA’ developed by Shellcase, Ltd., Israel.
FIG. 1A shows a silicon wafer 1 in which a number of IC chips 10a and 10b are formed. A scribe region 13 divides the adjacent chip 10a and 10b. Each chip 10a, 10b has a plurality of chip pads 12 on its active surface 11. Except for the chip pads 12, the active surface 11 is covered with a passivation layer 16. A pad extension layer 14 is connected with and extended from the chip pads 12.
FIG. 1B shows a step of attaching a first glass substrate 20 to the silicon wafer 1. For attachment between them, an epoxy 18 is coated on the passivation layer 16 and the pad extension layer 14.
FIG. 1C shows a step of forming ball pads 22 on the first glass substrate 20. The ball pads 22 are locations where solder balls will be formed as external connection terminals of the package.
FIG. 1D shows a step of forming a notch 24 by partially removing the wafer 1 from the first glass substrate 20 to upper parts of the chip 10a and 10b along the scribe region 13. As a result, a side end of the pad extension layer 14 is exposed to the notch 24.
FIG. 1E shows a step of forming a patterned lead layer 26, which is arranged from a surface of the notch 24 and to the ball pad 22. The lead layer 26 is therefore connected to the pad extension layer 14 exposed to the notch 24.
FIG. 1F shows a step of forming a solder mask layer 30, which covers most parts of the lead layer 26 except for parts on the ball pads 22.
FIG. 1G shows a step of forming solder balls 32 on the respective ball pads 22. The lead layer 26 on the ball pads 22 is therefore electrically coupled to the solder balls 32.
FIG. 1H shows a wafer back-grinding step. In this step lower parts of the wafer 1 are mechanically grinded, so each chip 10a and 10b is reduced in thickness.
FIG. 1I shows a step of etching away the wafer 1 along the scribe region 13 from the back surface of the wafer 1.
FIG. 1J shows a step of attaching a second glass substrate 34 to the back surface of the wafer 1 through an epoxy 36.
FIG. 1K shows a wafer-dicing step. In this step the wafer 1 is divided along a dicing region 38 within the scribe region 13, so the WLPs fabricated on the respective chips 10a and 10b are obtained.
As discussed hereinbefore, the conventional WLP employs the notch formed along the scribe region to allow forming the patterned lead layer through the notch. Accordingly, in order to form the notch, the conventional WLP needs an increase in width of the scribe region than the dicing region. Unfortunately, this may cause a decrease in chip count in a single wafer.
Additionally, since the patterned lead layer is formed on the exterior of the chip, the conventional WLP may reach the limits of a reduction in package size. Moreover, the patterned lead layer directly running on the chip edges only may restrict the pattern design flexibility.